De­sign Through Ver­ilog HDL

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This book is an at­tempt to ad­dress the is­sues of writ­ing test benches, test­ing a de­sign for all its de­sired func­tions, and iden­ti­fy­ing and re­mov­ing faults. It dis­cusses the con­structs in Ver­ilog through il­lus­tra­tive ex­am­ples. The ex­am­ples are tested with pop­u­lar and com­monly used sim­u­la­tion pack­ages and the re­sults re­pro­duced.

There are to­tal twelve chap­ters. Chap­ters 1 and 2 and brings out place and sig­nif­i­cance of Ver­ilog in very- large- scale in­te­gra­tion de­sign and ba­sics of the lan­guage, its con­ven­tion, etc. Chap­ters 4 and 5 form in­tro­duc­tion to de­sign through Ver­ilog. Chap­ter 6 is ded­i­cated to de­sign at the data flow level and chap­ters 7 and 8 dis­cuss be­havioural level de­sign.

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