Design Through Verilog HDL
This book is an attempt to address the issues of writing test benches, testing a design for all its desired functions, and identifying and removing faults. It discusses the constructs in Verilog through illustrative examples. The examples are tested with popular and commonly used simulation packages and the results reproduced.
There are total twelve chapters. Chapters 1 and 2 and brings out place and significance of Verilog in very- large- scale integration design and basics of the language, its convention, etc. Chapters 4 and 5 form introduction to design through Verilog. Chapter 6 is dedicated to design at the data flow level and chapters 7 and 8 discuss behavioural level design.