Merg­ing of EDA tools and hard­ware test plat­forms

Electronics For You - - TEST & - The au­thor is tech cor­re­spon­dent at EFY Ben­galuru

he ex­tremely com­pet­i­tive en­vi­ron­ment in which elec­tron­ics com­pa­nies work now is shown by how nextgen­er­a­tion com­mu­ni­ca­tion pro­to­cols are barely la­beled as stan­dards be­fore they can be seen in the mar­ket. For in­stance, the 802.11ac so­lu­tions have al­ready been brought out by Broad­com sit­u­a­tions like these, com­pa­nies go all out to get a jump­start on the com­pe­ti­tion, and what bet­ter way to do this than to merge de­sign and test­ing in or­der to ac­cel­er­ate the ‘time to mar­ket’.

Adesh Jain, ap­pli­ca­tions con­sul­tant at Agi­lent Tech­nolo­gies, ex­plains why the tra­di­tional method is slow: “Tra­di­tion­ally, for any com­plete elec­tronic prod­uct to be ready for the mar­ket, each compo tools, then pro­to­types are fabri prod­uct is re­leased to the mar­ket. If dis­crep­an­cies are found in the hard­ware at later stages, the whole cy­cle has to be re­peated, which would re­sult in loss of time as well as money for any or­gan­i­sa­tion.”

Proper ver­i­fi­ca­tion at ear­lier stages re­duces this time and ef­fort to a great ex­tent. The tests, specs, al­go­rithms and plots used in the early stages of EDA are the same as mea­sured on the test bench. The aim is to merge both the worlds and see if it is pos­si­ble to save the de­sign engi and thus im­prove pro­duc­tiv­ity while re­duc­ing the time to get the prod­uct out to the mar­ket.

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