ULTRA-WIDE BANDWIDTH AND POWER EFFICIENCY
While these HBM stacks are not physically integrated onto the GPU die, they are so closely connected that they are almost indistinguishable from on-die integrated RAM. This close proximity enables extremely wide memory bus widths, and consequently allows much lower memory clock speeds to be used to achieve the required performance.
This is because with GDDR5 memory, individual DRAM chips are placed side by side and connected via long copper traces on the PCB. However, HBM dies are so close to the GPU that the traces that connect them are much shorter, which thus enables much wider memory bus widths.
On the AMD Radeon R9 Fury X and Fury, each HBM tower has a 1,024-bit memory bus width, and the four towers flanking the GPU die combine for a 4,096-bit bus width, the highest on any GPU so far. From buses just hundreds of bits wide, we've rocketed to seeing figures in the thousands, and this is just a first-generation product.
Both of AMD's HBM-equipped GPUs have a 512GB/s of memory bandwidth, beating even the 336.5GB/s of the NVIDIA GeForce GTX TITAN X.
Power consumption is also much reduced because the closer proximity enables more efficient communication between the memory and GPU. Input voltage is down to 1.3V, from 1.5V on traditional GDDR5 memory.