In­tel clings to Moore’s Law

In­tel is chang­ing the way it mea­sures process tech­nol­ogy ad­vance­ments, re­veals Agam Shah

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In­tel’s re­for­mu­la­tion of Moore’s Law met­rics is an at­tempt by the com­pany to make up for lost time and a messy move to the 14nm process from the pre­vi­ous 22nm process

The land­mark Moore’s Law ob­ser­va­tion, which is now more than 50 years old, keeps shape shift­ing as the phys­i­cal chal­lenges of mak­ing smaller chips mounts.

Many sci­en­tists agree that Moore’s Law is dy­ing (page 15), but In­tel is cling­ing on to it for dear life. It has been its guid­ing light for mak­ing chips smaller, faster and cheaper.

Now, the firm is chang­ing the way it mea­sures process tech­nol­ogy ad­vance­ments, which will help the com­pany con­tinue to boast about hit­ting key Moore’s Law met­rics in terms of eco­nomics and the shrink­ing of chip sizes. Pri­mar­ily, the com­pany is chang­ing the way it mea­sures logic tran­sis­tor den­sity, us­ing a wider cell width.

“Moore’s Law is not dead, at least not for us,” said Stacy Smith, In­tel’s ex­ec­u­tive vice pres­i­dent lead­ing man­u­fac­tur­ing, op­er­a­tions and sales, dur­ing an event to talk about man­u­fac­tur­ing in San Francisco re­cently.

At its heart, Moore’s Law states that the cost of mak­ing chips goes down while the ca­pa­bil­i­ties go up. In­tel’s in­ter­pre­ta­tion of Moore’s Law has changed mul­ti­ple times. Ini­tially, the chip­maker was doubling tran­sis­tors ev­ery 18 months, which then ex­panded to two years. On its most re­cent 14nm process, that time line ex­panded to three years.

With the new mea­sure­ments, In­tel will be able to boast that its man­u­fac­tur­ing im­prove­ments are sur­pass­ing Moore’s Law. The com­pany also said it would cut the man­u­fac­tur­ing cost per tran­sis­tor by half with each new man­u­fac­tur­ing process, which is in line with Moore’s Law.

But there are caveats to the new met­rics. In­tel is mak­ing mul­ti­ple changes and in­tro­duc­ing more chip ar­chi­tec­tures on each man­u­fac­tur­ing process, and ad­vanc­ing to new pro­cesses at a slower pace.

Later this year, the firm will start mak­ing chips us­ing the 10nm process, which is be­ing pro­jected to last for roughly three years. Af­ter that the com­pany will move to 7nm, and Smith said there is ‘vis­i­bil­ity’ to the 5nm process.

Ri­val fabs are now catch­ing up with In­tel, which had a man­u­fac­tur­ing ad­van­tage for more than a decade. Sam­sung is mak­ing 10nm chips for mo­bile de­vices, with one ex­am­ple be­ing Qual­comm’s Snap­dragon 835, though In­tel says its lat­est 14nm chips are as good as the 10nm of­fer­ings from Sam­sung and Glob­alFoundries.

The firm’s re­for­mu­la­tion of Moore’s Law met­rics is an at­tempt by the com­pany to make up for lost time and a messy move to the 14nm process from the pre­vi­ous 22nm process, said Nathan Brook­wood, prin­ci­pal an­a­lyst at In­sight 64, who was at the event.

Man­u­fac­tur­ing is­sues on 14nm in early 2014 meant In­tel couldn’t achieve the cost or tran­sis­tor den­sity it wanted. As the 14nm process ma­tured, In­tel started hit­ting those met­rics, and had to press the restart but­ton on its Moore’s Law pro­jec­tions. Chip ad­vances have also con­trib­uted to re­con­sid­er­a­tion of the met­rics.

“There is an amount of rea­son­able­ness to it,” Brook­wood ar­gued, say­ing In­tel re­mains ahead of ri­vals on chip den­sity. In­tel has an ad­van­tage on gate and metal pitches, giv­ing its chips more den­sity. In­tel will con­tinue to de­liver new PC and server chip ar­chi­tec­tures ev­ery year, with a min­i­mum 15 per­cent per­for­mance im­prove­ment per gen­er­a­tion. Com­ing next will be eight-gen­er­a­tion Core chips made on the 14nm process, an un­prece­dented fourth chip ar­chi­tec­ture on the process tech­nol­ogy. In­tel will also be re­leas­ing PC chips co­de­named Can­non Lake based on the 10nm process later this year.

That could cre­ate a sce­nario where the chip­maker has 14- and 10nm PC chips hit­ting the mar­ket at the same time. That could cre­ate is­sues in the brand­ing of chips and con­fu­sion among buy­ers look­ing to ac­quire the lat­est and great­est In­tel pro­ces­sors.

Ear­lier this year In­tel said it will stress per­for­mance ben­e­fits to chip buy­ers, while play­ing down the role of process tech­nol­ogy.

For the past few years, In­tel has moved away from the once-fa­mous ‘tick-tock’ scal­ing, where new pro­cesses were ‘ticks’ and new ar­chi­tec­tures were ‘tocks’. It is switch­ing to what the com­pany calls ‘hy­per­scal­ing’ ad­vances, a new metaphor an­nounced at the event to de­scribe man­u­fac­tur­ing ad­vances. In­tel will now use the ‘+’ and ‘++’ sym­bols to mark ad­vances in the 14- and 10nm pro­cesses.

Hy­per­scal­ing will help In­tel cram new ar­chi­tec­tural and process in­no­va­tions with­out hur­ry­ing a move to a new man­u­fac­tur­ing process.

New lithog­ra­phy tech­niques such as quad-pat­tern­ing will help In­tel take ad­van­tage of the eco­nomic ben­e­fits de­scribed by Moore’s Law, ex­plained Kaizad Mistry, vice pres­i­dent and co-di­rec­tor of logic tech­nol­ogy devel­op­ment at In­tel. That will im­prove tran­sis­tor den­sity, which also brings per­for­mance and power-ef­fi­ciency en­hance­ments. In­tel is pro­ject­ing 15 per­cent im­prove­ments in per­for­mance with each ad­vance in the 10nm ‘+’ and ‘++’ pro­cesses. In­tel will also re­duce the chip size to pack I/O, logic and SRAM blocks into a much smaller area.

In­tel is do­ing what the com­pany calls “ag­gres­sive pitch scal­ing”, which in­volves pack­ing wires, tran­sis­tors and 3D fins closer to­gether. On the 10nm process, that helps pro­vide tran­sis­tor den­sity im­prove­ment that is 2.7 times bet­ter than the 14nm process.

The chip­maker is also bring­ing the abil­ity to mix and match dif­fer­ent cores into an in­te­grated sys­tem-on-chip. The cores could be made us­ing dif­fer­ent man­u­fac­tur­ing pro­cesses. It’s also much how ARM chips are de­signed and made, a process that in­te­grates CPUs, modems, graph­ics pro­ces­sors and other cores into a sin­gle chip.

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