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In­tel could tap a new high-speed in­ter­con­nect to join dif­fer­ent chips to­gether to make fu­ture CPUs, writes Gor­don Mah Ung

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To­day’s pro­ces­sors, made us­ing a sin­gle con­tin­u­ous slab of sil­i­con, may soon give way to mul­ti­ple chips in­ter­con­nected at high speeds, In­tel re­cently re­ported.

The chip­maker said that its new Embed­ded Multi-die In­ter­con­nect Bridge, or EMIB, tech­nol­ogy would let a 22nm chip con­nect to a 10nm pro­ces­sor and a 14nm one, all on the same pro­ces­sor.

“For ex­am­ple, we can mix high­per­for­mance blocks of sil­i­con and IP to­gether with low-power el­e­ments made from dif­fer­ent nodes for ex­treme op­ti­mi­sa­tion,” said In­tel’s Murthy Ren­duch­in­tala, who heads the Client, IoT and Sys­tems Ar­chi­tec­ture Group.

That’s a rad­i­cal de­par­ture from how the com­pany has con­structed most CPUs and SoCs, where all com­po­nents of a CPU

or SoC are built on the same process. Ren­duch­in­tala didn’t com­mit EMIB to any par­tic­u­lar up­com­ing SoC or CPU, but said it was clear the tech would play a large role in near- and long-term prod­ucts from In­tel. He added that EMIB can hit “multi hun­dreds of gi­ga­bytes” speeds while re­duc­ing la­tency by four times over tra­di­tional mul­ti­chip tech­niques. “It’s truly a trans­for­ma­tional tech­nol­ogy for In­tel,” he said.

With EMIB, In­tel could build the CPU and graph­ics cores on a bleed­ing-edge 10nm process and keep lower-per­for­mance com­po­nents on 14nm. Still other parts that might ac­tu­ally ben­e­fit from be­ing fabbed on, say, the 22nm process, such as power cir­cuits, could stick to the larger process. At one point In­tel dab­bled with in­te­grat­ing the volt­age reg­u­la­tion into the CPU with its fourth-gen­er­a­tion Haswell and fifth-gen­er­a­tion Broad­well chips. With sixth-gen­er­a­tion Sky­lake and sev­enth-gen­er­a­tion Kaby Lake though, the in­te­grated volt­age reg­u­la­tion was yanked, which some be­lieved was due to prob­lems scal­ing the fully in­te­grated volt­age reg­u­la­tor down to 14nm. An EMIB ver­sion could po­ten­tially keep the FIVR at 22nm.

This isn’t the first time that In­tel has con­sid­ered fus­ing two chips to­gether in one CPU. The orig­i­nal Pen­tium Pro de­sign was a mul­ti­chip pack­age as was the Core 2 Quad se­ries of CPUs.

EMIB is far more ad­vanced though, and is con­structed within the sil­i­con it­self. A tra­di­tional mul­ti­chip pack­age de­sign runs wires through the sub­strate that the chips are mounted to. That lim­its the amount of wires and speeds they can run at.

An­other method is to use a sil­i­con in­ter­poser to con­nect the dies. While this yields high wire den­sity and high per­for­mance, it’s ex­pen­sive to man­u­fac­turer.

EMIB es­sen­tially makes it far eas­ier to com­bine chips with­out giv­ing up much of the per­for­mance. Al­though In­tel made a point of high­light­ing EMIB at its tech­nol­ogy and man­u­fac­tur­ing day for press and fi­nan­cial an­a­lysts, this isn’t EMIB’s first use. In­tel ac­tu­ally in­tro­duced it with the Al­tera Stratix 10, which used EMID to con­struct the SoC.

To­day’s CPUs are mono­lithic de­signs with all of the func­tion­al­ity built on the same process tech­nol­ogy

In­tel is al­ready fab­bing the Al­tera Stratix 10 by join­ing to­gether mul­ti­ple chips us­ing its new EMIB in­ter­con­nect

Fu­ture CPUs from In­tel could fuse to­gether mul­ti­ple process tech­nolo­gies

In­tel says its Embed­ded Multi-die In­ter­con­nect Bridge is more cost ef­fec­tive than meth­ods that use an in­ter­poser to con­nect chips and of­fers far bet­ter per­for­mance than mul­ti­chip pack­age de­signs

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