3D stacking: The next frontier for chip technology?
AMD’s V-cache technology is a big step forward.
Computex may have been virtual in 2021, but that didn’t stop AMD from making a big splash during its keynote. On top of the announcements of its Ryzen 5000-series APUs and its long awaited FidelityFX Super Resolution tech came the announcement of its 3D V-Cache stacking technology. It was more than an announcement though – AMD demonstrated the technology, indicating that we could see a Zen 3 refresh incorporating V-Cache as soon as this year.
AMD has been on a roll over the last few years. The company released HBM GPUs, multi-chip module and chiplet processors, and now it’s taking the next step in its 3D packaging journey. Stacked cores may not be here yet but stacked cache is. AMD CEO Dr Lisa Su demonstrated a Ryzen 5900X prototype with 192MB of L3 cache, a 3x increase from the standard 64MB of the 5900X.
The design incorporates a separate 64MB die atop an 8-core complex with its 32MB of L3 cache. The dies are connected though direct copper-to-copper bonding. AMD claims that this cache has a total bandwidth of 2TB/s. To demonstrate the gains on offer, AMD showed a selection of games, comparing both the standard 5900X and the prototype 5900X with V-Cache. Both CPUs were clocked at 4GHz, with the result being an average 15 per cent uplift in gaming performance. We’d take these numbers with a grain of salt, but when you add this to the expected performance uplift we can expect from the Zen 4 architecture, plus things like 5nm and its expected power efficiency, and it’s clear that AMD is well placed to compete against Intel’s Alder Lake and Raptor Lake series of processors.
There are some unanswered questions though. AMD was
A life-long PC tech enthusiast, Chris has worked acoss the industry in many areas as a product and technology expert.
keen to emphasise the gaming gains the technology offers, as it did with the move from Zen 2 to Zen 3. Not all workloads will benefit from such large caches. Power consumption woes aside, Intel is still very competitive with its relatively tiny L3 caches while remaining competitive in gaming.
Will enterprise workloads see much benefit? If they are coded to, of course, but have to wait and see just how real workloads react to such massive amounts of cache.
The possibilities on offer from 3D stacking are very exciting. How about an RDNA2 APU with 3D-cache? That could really elevate mobile GPU performance with only a minor power consumption penalty and remove DRAM speed as the bottleneck of its GPU performance. Would it be like Infinity cache on steroids? How about an Epyc processor with 192 or 256 cores or more? These are crazy numbers and the Googles, Amazons and Facebooks of the world will be lining up with chequebooks open.
Could true 3D stacked chiplets be something of a holy grail of processor manufacturing? It’s well known that node shrinks are becoming more and more difficult. Dies are typically measured in the X and Y axis though. What about the Z-axis? If thermals can be controlled, then there’s no insurmountable reason why we won’t see core counts and cache sizes continue to rise for the foreseeable future. We could be looking at the first steps on an exciting new path.
We’re really looking forward to seeing what Intel can do with Alder Lake and its Big/Little architecture shift. It may need to pull out something special to keep pace with an ever increasingly confident and innovative AMD.
“Stacked cores may not be here yet but stacked cache is. AMD CEO Dr Lisa Su demonstrated a Ryzen 5900X prototype with 192MB of L3 cache, a 3x increase from the standard 64MB of the 5900X.”