RISC-V IS NOT RISC-V

RISC-V is a catch-all term encompassing multiple architectures. Our GigaDevice GD32VF103 RVSTAR is 32-bit RISC-V Core, which is optimised for control applications and does not have functionality such as an MMU required for advanced operating systems.

This should not be considered indicative of the RISC-V standard as a whole. Various options are available, permitting chip designers to customise the compute core to their needs. Eliminating unnecessary functionality leads to smaller (and cheaper) die sizes; lower power consumption is achieved by the smaller number of transistors.

In particular, various integer instruction sets are available, permitting chip designers the creation of semiconductors better suited to the needs of advanced (desktop-like) processors. These already exist, a good (low-priced) example being the AllWinner D1s. It uses a Xuantie C906 core and can run Linux out of the box.

While a detailed analysis of the RISC-V standard exceeds the scope of this article, permit us to recommend Computer Organization and Design RISC-V Edition by Hennessy and Patterson. While quite theoretical, it provides an excellent overview.

Furthermore, keep in mind that RISC-V usage does not necessarily equal lower total cost of ownership. The rumour mill reports that ARM is more than willing to cut deals on licensing if pressured – in combination with the economies of scale enabled by larger-scale production, a RISC-V-based design could turn out to be more expensive than an equivalent system based on an ARM core.