We can’t em­pha­size enough that bench­marks are largely ir­rel­e­vant at this point, as RISC-V im­ple­men­ta­tions are go­ing to be tar­get­ing em­bed­ded, low-power, con­troller and en­thu­si­ast boards. No one is go­ing to be re­leas­ing a con­sumer­level lap­top or desk­top at this early stage. There is a ques­tion, though, of how ef­fi­cient the ISA is ver­sus other com­mer­cial im­ple­men­ta­tions.

A thor­ough mi­cro-op anal­y­sis of, say, x86-64 ver­sus RISC-V com­piled bi­na­ries is the sort of thing good PhD th­e­ses are made from. In fact, that was ex­actly what was done back in 2016; you can see an out­line of the re­port on YouTube ( www.youtube.com/ watch?v=Ii_pEXKKYUg), which shows RISC-V bi­na­ries are com­pet­i­tive in mi­cro-op den­sity, and can out­per­form x86 and ARMv8 code, with a num­ber of po­ten­tial com­piler op­ti­miza­tions be­ing high­lighted from the study.

For a more lay­man’s level look, we’ll take the an­cient in­te­ger-based Dhry­s­tone bench­mark. It may be get­ting on a bit, but it’s been tweaked to mit­i­gate against hard­ware and com­piler cheats, while it’s suit­able to use as a rough guide for per­for­mance across dif­fer­ing hard­ware ar­chi­tec­tures.

The stan­dard mea­sure is mil­lions of Dhry­s­tones per MHz, aka DMIPS/MHz. It roughly scores how much work a sin­gle core can do per MHz clock. It ob­vi­ously doesn’t count ac­cel­er­ated vec­tor or SIMD in­struc­tions; think of it as a stan­dard pro­gram bench­mark. We’ve listed a range of pro­ces­sors—the one we find of in­ter­est is the Atom N455, as this is a mod­ern in-order x86 ar­chi­tec­ture. It clearly has work to do to catch up ARM; Cor­tex A53 is an eight-stage, dual-is­sue in-order ar­chi­tec­ture and, run­ning on the Rasp­berry Pi 3, is sig­nif­i­cantly faster.

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