SPEED AND BENCHMARKS

We can’t emphasize enough that benchmarks are largely irrelevant at this point, as RISC-V implementations are going to be targeting embedded, low-power, controller and enthusiast boards. No one is going to be releasing a consumerlevel laptop or desktop at this early stage. There is a question, though, of how efficient the ISA is versus other commercial implementations.

A thorough micro-op analysis of, say, x86-64 versus RISC-V compiled binaries is the sort of thing good PhD theses are made from. In fact, that was exactly what was done back in 2016; you can see an outline of the report on YouTube ( www.youtube.com/ watch?v=Ii_pEXKKYUg), which shows RISC-V binaries are competitive in micro-op density, and can outperform x86 and ARMv8 code, with a number of potential compiler optimizations being highlighted from the study.

For a more layman’s level look, we’ll take the ancient integer-based Dhrystone benchmark. It may be getting on a bit, but it’s been tweaked to mitigate against hardware and compiler cheats, while it’s suitable to use as a rough guide for performance across differing hardware architectures.

The standard measure is millions of Dhrystones per MHz, aka DMIPS/MHz. It roughly scores how much work a single core can do per MHz clock. It obviously doesn’t count accelerated vector or SIMD instructions; think of it as a standard program benchmark. We’ve listed a range of processors—the one we find of interest is the Atom N455, as this is a modern in-order x86 architecture. It clearly has work to do to catch up ARM; Cortex A53 is an eight-stage, dual-issue in-order architecture and, running on the Raspberry Pi 3, is significantly faster.