What AMD’S 64-core ‘Rome’ server CPU tells us about Ryzen 2
Rome features a ‘chiplet’ design with 7nm-based x86 cores surrounding a 14nm IO chip.
AMD’S Ryzen 2 consumer CPU isn’t coming until 2019, but we saw hints of what to expect in “Rome,” the 64-core server CPU AMD unveiled in early November. It’s based on a new 7nm Zen 2 core that’s likely to find its way into Ryzen 2 next year. Let’s take a closer look.
Each Rome CPU will feature 64 cores with symmetrical multi-threading for 128 threads per socket. The CPU itself is “revolutionary,” AMD said, and is built around eight separate 7nm “chiplets” with eight cores each.
The chipsets contain no memory controller or PCIE, but are instead tied to a central IO chip built on 14nm. The IO chip has 8 channels of DDR4 plus support for PCIE 4.0. The company connects each chiplet to the IO
chip via a 2nd-generation reduced latency Infinity Fabric.
The chiplet isn’t the only new feature. AMD said it reworked the Zen 2 core to offer double the throughput, increased floating point performance, a doubled core density and half the energy use per operation of Zen. Compared to Zen, AMD said to expect twice the performance and four times the floating point performance per socket. Just the process improvements alone would give it a 1.25x performance bump if the power consumption were kept the same, the company said.
And yes, it’s fast. AMD showed a preproduction, air-cooled, non-overclocked Rome outperforming a dual-socket Skylake SP with 56 cores and 112 threads in the floating-point intensive C-ray benchmark ( go.pcworld.com/cray).
SO WHAT DOES THAT MEAN FOR RYZEN 2?
What’s not known is how much of the Rome DNA will make it into the consumer Ryzen 2 due early next year. At a minimum, we’d expect the same 8-core chiplets to be scaled down for desktop use. All of the front-end improvements, floating point performance, and efficiencies of the 7nm process are likely to make it a mean CPU.
“By using the Zen 2 architecture and 7nm, on desktops,” said analyst Pat Moorhead of Moor Insights. “I am expecting improved raw core performance with frequency and IPC improvements positively impacting lower