Design of a High Speed Low Power Time-to-digital Converter Based on Multi-stage Amplification Structure

FAN Chuanqi1, JIA Song2,†, WANG Zhenyu1, YAN Wei1, WU Zebo1

1. School of Software and Microelectronics, Peking University, Beijing 100871; 2. Key Laboratory of Microelectronics Devices and Circuits (MOE), School of Electronics Engineering and Computer Science, Peking University, Beijing 100871; † Corresponding author, E-mail: jias@pku.edu.cn

Abstract The authors present a time-to-digital converter based on multi-stage amplification structure. This structure consists of coarse stage and fine stage. Coarse stage utilizes delay line to get the residue which is less than a buffer’s delay. A small area and low power residue selecting logic is designed. In the fine stage, 2× time amplifier and half judger is utilized to generate 4 binary codes from MSB to LSB. Simulation in SMIC 65 nm process shows that the new structure has a high conversion speed up to 470 MS/S and power consumption is 1.3 mw at 100 MHZ with the resolution of 1.44 ps and range of 736 ps. An accurate gain robust to PVT variation can be achieved with the calibration of the time amplifier, so a good integral nonlinearity is obtained. Key words time-to-digital converter; time amplifier; high speed; low power

时间数字转换器(time-to-digital converter)是将两个信号的上升沿时间差用数字量化的电路, 广泛应用于全数字锁相环(ADPLL)、时间域 ADC 以及各种测量时间间隔的设备中。与模拟方法相比, 基于数字电路的时间数字转换器面积小, 功耗低, 稳定性强, 集成度高。随着 CMOS 工艺的不断发展,越来越多的设计被数字模块取代。延时链 TDC 是目前主流的采用数字方法设计的 TDC, 由一串延时单元组成的延时链组成, 能够达到一个延时单元的

精度。为了实现更高的精度, 游标型(vernier) TDC、时间放大器(time amplifier) TDC、门控环形振荡器(gated ring oscillator) TDC 和脉冲衰减型 (pulseshrinking) TDC 等被提出[1]。游标型 TDC[2] (图 1)的start 和 stop 两个上升沿分别经过1和2两种不同的延时单元, 分辨率为1–2。为了得到更大的量程,就需要很多延时单元, 会带来转换速率低和功耗大的问题。时间放大器 TDC[3] (图 2)是一种两级的TDC 结构, 粗测阶段经过一串延时单元, 粗测后的