Low Resource Consumption Design of Digital Decimation Filter

QIAN Zebin, YAN Wei†

School of Software & Microelectronics, Peking University, Beijing 100871; † Corresponding author, E-mail: yanwei@ss.pku.edu.cn

Abstract A digital decimation filter applied to audio Sigma-delta ADC is designed. The filter adopts the design of multi-stage and multi-rate down sampling structure, in-band ripple of decimation filter is less than 0.06 db overall, bandwidth is 21.6 khz, minimum working frequency is 10 MHZ. Through the innovation of filter hardware architecture design, it effectively reduces the filter circuit area and power consumption. Chip test results show that the SNR is above 87.2 db when processing PDM signals is at the down sampling rate of 64, 4 order Sigma-delta modulation. Designed in SMIC’S 0.13 μm CMOS process, the decimation filter area is 0.146 mm2. Filter area is reduced by 58%, and power consumption is reduced by over 60% compared with the same type decimation filters. Key words decimation filter; Sigma-delta; small area; low power consumption

过采样 Sigma-delta 模数转换器常用于音频信号的高精度模数转换。抽取滤波器是过采样 Sigmadelta模数转换器的重要组成部分, 其作用是对调制器输出的脉冲密度调制信号进行解码处理, 滤除基带信号带外噪声, 降低采样率至奈奎斯特频率,并从调制器输出的高速低分辨率的数字信号中重构出低速高分辨率的数字信号。该滤波器设计的优劣直接影响最后得到的音频数据的性能。

[1]为了实现高效低资源抽取滤波, Crochiere 等提出一种级联积分梳状滤波器(cascade integrator comb filter, CIC), 但是通带滚降过大。Hogenauer

[2]等 提出多级滤波器结构, 通过 FIR 滤波器补偿

CIC滤波器的通带滚降。为进一步提高抽取滤波器的通带和阻带性能, 马绍宇等[3]引入半带滤波器滤除带外噪声, 但 FIR 滤波器与半带滤波器的阶数较高, 也没有滤除 Sigma-delta 调制固有的直流增益。由于 FIR滤波器与半带滤波器所需乘法器数量大, 导致芯片数字电路面积大。本文基于抽取滤波器多级多采样率结构, 对抽取滤波器进行理论分析,同时提出一种新型的小面积、低功耗的抽取滤波器硬件架构。

1 解码滤波器整体结构

处理过采样脉冲密度调制信号时, 第一级通常