Design and Implementation of an Asynchronous Low Power RSA Circuit Structure

ZHANG Qihui, CAO Jian, CAO Xixin, YU Dunshan, ZHANG Xing†

ACTA Scientiarum Naturalium Universitatis Pekinensis - - CONTENTS - ZHANG Qihui, CAO Jian, CAO Xixin, et al

School of Software and Microelectronics, Peking University, Beijing 102600; † Corresponding author, E-mail: [email protected]

Abstract An asynchronous low power RSA circuit structure and its modular multiplication circuit structure for smart cards and RFID tags are proposed. By using GTECH optimization scheme and Brzcallmux implementation strategy, ASIC implementation is carried out based on a TSMC 130 nm standard CMOS technology. Experimental results show that the area of the proposed asynchronous low power RSA is only 4% of that of another asynchronous RSA, its average time to perform a cryptographic operation is only 0.216% of that of another asynchronous RSA, and its power consumption is only 16.99% of that of its corresponding synchronous counterpart. Key words asynchronous; low energy; RSA; GTECH; ASIC

Newspapers in Chinese (Simplified)

Newspapers from China

© PressReader. All rights reserved.