Hardware architecture

ThH 6P, dHYLFHV OLNH flDVh PHPoULHV, WouFh-VFUHHnV Dnd some authentication devices are usually not connected to the CPU directly. Instead, another chip like the PCH (Platform Controller Hub) mediates between the CPU and the SPI device. The PCH is a family of Intel microchips. It is the successor to the previous Intel Hub Architecture, which uVHd WhH noUWhEULdgH Dnd WhH VouWhEULdgH LnVWHDd, Dnd fiUVW appeared in the Intel 5 Series.

The PCH controls certain data paths and support functions used in conjunction with Intel CPUs. The I/O functions are reassigned between this new central hub and the CPU in comparison to the previous architecture, wherein some northbridge functions like the memory controller and PCI-e lanes were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.

Figure 1 shows a typical hardware connection. The CPU talks to the PCH through the PCI interface. The PCH contains a SPI controller that talks to the flash chip through the SPI interface.

all such MTD devices. Figure 2 shows one such example. As shown in Figure 2, to access the SPI flash chip, several layers like mtdchar, the MTD subsystem, chip driver, SPI framework and SPI controller are involved. Although it may look complex initially, the layered design makes it simple and possible to access any kind of MTD device in any manner. For example, if an MTD device is to be accessed as a block device rather than a character device, then the mtdchar layer can be replaced by the Linux VFS, Block I/O and blockdev layers. The blockdev layer provides a flash translation layer that emulates the MTD device as a block device. Therefore, it is possible to use disk-based file systems like ext2 and FAT on the MTD device. Similarly, if an SPI flash chip is replaced by a CFI flash chip, then the chip driver layer is changed to an appropriate chip driver (like cfi_cmdset_0001.c). In the same manner, if a Winbond SPI flash is replaced by a Micron SPI flash, then the SPI controller layer should be changed. Therefore, the layered architecture provides reusable components that make it easy to access any kind of MTD device. The only layer that is never changed is the MTD sub-system layer, which is responsible for providing a unified and uniform layer that enables a seamless combination of low-level MTD chip drivers with higher-level interfaces.

Each layer has an assigned job. The chip driver has the UHVSonVLELOLWy oI LPSOHPHnWLng WhH FhLS-VSHFLfiF SUoWoFoO. ThHUHIoUH, WhHUH DUH dLIIHUHnW FhLS dULYHUV IoU 6P, flDVhHV Dnd C), flDVhHV EHFDuVH HDFh oI WhHP IoOOowV D dLIIHUHnW protocol. This protocol consists of command sets and oSFodHV undHUVWood Ey WhH flDVh FhLS. ThH 6P, IUDPHwoUN is a common layer for all SPI devices. This layer has the responsibility of mediating between the chip driver and the controller driver as you will see later in this article. The SPI controller layer is responsible for actual communication to the SPI device. Therefore, for every unique SPI device, there has to be a SPI controller driver. So let’s focus on such SPI FonWUoOOHU dULYHUV IoU 6P, flDVh PHPoUy.