TSMC mulls advanced chip packaging capacity in Japan

TOKYO (Reuters) — Taiwan’s TSMC is looking at building advanced packaging capacity in Japan, according to two sources familiar with the matter, a move that would add momentum to Japan’s efforts to reboot its semiconductor industry.

The deliberations are at an early stage, they added, declining to be identified as the information was not public.

One option the chipmaking giant is considering is bringing its chip on wafer on substrate (CoWoS) packaging technology to Japan, according to one of the sources who was briefed on the matter.

CoWoS is a high-precision technology that involves stacking chips on top of each other, boosting processing power while saving space and reducing power consumption.

Currently, all of TSMC’s CoWoS capacity is in Taiwan.

No decisions on the scale of or the timeline for a potential investment have been made, the source said.

TSMC, formally known as Taiwan Semiconductor Manufacturing Co., declined to comment.

Demand for advanced semiconductor packaging has surged globally in tandem with the artificial intelligence boom, spurring chipmakers including TSMC, Samsung Electronics and Intel, to boost capacity.

TSMC Chief Executive C.C. Wei said in January that the company plans to double CoWos output this year with further increases slated in 2025.

On Monday, TSMC said it was planning additional advanced packaging capacity in Chiayi in southern Taiwan to respond to strong market demand, without giving details.

Construction of a new Chiayi CoWoS plant is due to start in early May, the island’s official Central News Agency quoted Vice Premier Cheng Wen-tsan as saying.

Building capacity for advanced packaging would extend TSMC’s growing operations in Japan where it has just built one plant and announced another — both on the southern island of Kyushu, a chipmaking hub.