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Intel could tap a new high-speed interconnect to join different chips together to make future CPUs, writes Gordon Mah Ung
Today’s processors, made using a single continuous slab of silicon, may soon give way to multiple chips interconnected at high speeds, Intel recently reported.
The chipmaker said that its new Embedded Multi-die Interconnect Bridge, or EMIB, technology would let a 22nm chip connect to a 10nm processor and a 14nm one, all on the same processor.
“For example, we can mix highperformance blocks of silicon and IP together with low-power elements made from different nodes for extreme optimisation,” said Intel’s Murthy Renduchintala, who heads the Client, IoT and Systems Architecture Group.
That’s a radical departure from how the company has constructed most CPUs and SoCs, where all components of a CPU
or SoC are built on the same process. Renduchintala didn’t commit EMIB to any particular upcoming SoC or CPU, but said it was clear the tech would play a large role in near- and long-term products from Intel. He added that EMIB can hit “multi hundreds of gigabytes” speeds while reducing latency by four times over traditional multichip techniques. “It’s truly a transformational technology for Intel,” he said.
With EMIB, Intel could build the CPU and graphics cores on a bleeding-edge 10nm process and keep lower-performance components on 14nm. Still other parts that might actually benefit from being fabbed on, say, the 22nm process, such as power circuits, could stick to the larger process. At one point Intel dabbled with integrating the voltage regulation into the CPU with its fourth-generation Haswell and fifth-generation Broadwell chips. With sixth-generation Skylake and seventh-generation Kaby Lake though, the integrated voltage regulation was yanked, which some believed was due to problems scaling the fully integrated voltage regulator down to 14nm. An EMIB version could potentially keep the FIVR at 22nm.
This isn’t the first time that Intel has considered fusing two chips together in one CPU. The original Pentium Pro design was a multichip package as was the Core 2 Quad series of CPUs.
EMIB is far more advanced though, and is constructed within the silicon itself. A traditional multichip package design runs wires through the substrate that the chips are mounted to. That limits the amount of wires and speeds they can run at.
Another method is to use a silicon interposer to connect the dies. While this yields high wire density and high performance, it’s expensive to manufacturer.
EMIB essentially makes it far easier to combine chips without giving up much of the performance. Although Intel made a point of highlighting EMIB at its technology and manufacturing day for press and financial analysts, this isn’t EMIB’s first use. Intel actually introduced it with the Altera Stratix 10, which used EMID to construct the SoC.