INTERFACE CONNECTION ADVANCEMENTS
Where will the world of interconnectivity take us?
RUMORS ABOUND that PCIe 4.0 is coming to the masses. Perhaps not in the early part of the new year, but you can bet it’ll be here by the end of 2019. Announced in 2016, and ratified by PCI-SIG ( a super-conglomerate of over 900 companies, including Intel, AMD, Dell, HP, and IBM) in the summer of 2017, PCIe 4.0 should have already been in production and on mainstream boards sometime in 2018. However, with a lack of support on the processor side of things, and there seemingly not being a need for the connection standard, delayed implementation and progress on introducing the spec has stagnated. We just didn’t need it. Until now.
If Threadripper and Ryzen 3 follow the same or a similar specification as that of EPYC 2, both processor lineups should see support for PCIe 4.0 included as standard, with Intel also likely to follow suit with its 10nm parts. And with it being backward compatible, not including it on the next generation of motherboards would simply be ridiculous.
What’s so great about PCIe 4.0? For starters, it doubles the per-pin raw bitrate, increasing from 8GT/s to 16GT/s. It also comes packing a reduction in overall system latency, along with improved flexibility and lane-width configurations for developers who are interested in tapping it up for lower-power applications and devices.
The big one for us, however, is that increased data rate. 16GT/s per lane should enable PCIe x4 devices to operate at up to speeds of about 6.4GB/s, versus the 3.2GB/s cap we’re at now, giving us a lot more headroom for flash storage devices, and hopefully improving CPU-GPU communication and performance in multi-card situations, especially at higher resolutions. The latter is less of a problem for Nvidia, with its NVLink, of course, but for AMD, it’s a pretty big deal, especially if the company gets back into the highend GPU game with Navi.
PCI-SIG has also teased us with PCIe 5.0. Although complete specifications are sparse right now, we do know that it will be another doubling of the bandwidth limitations, meaning 32GT/s per lane, or 12.8GB/s theoretical maximum for transfer speeds on flash devices, and a staggering 128GB/s bandwidth for something like a 16-slot GPU.
The big question is how will these standards be introduced—if at all? Opinion in the office is split. The first camp, rooting for PCIe 4.0, reckons that thanks to EPYC 2’s integration of PCIe 4.0, it wouldn’t make a ton of sense to develop and assemble two separate processor designs, when you could produce one and disable some of the cores. Thus, as PCIe 4.0 is backward compatible with the other generations, adding it is a fairly easy task.
The other camp, the skippers, reckons that the bandwidth provided by PCIe 4.0 simply isn’t enough, and because it takes both time and money to validate a spec like this (bear in mind that PCIe 5.0 has already been announced, and is due for launch in 2020), why bother, when we’ll just need to do the same again in 2021? It’s a tricky one, and only time will tell.
NVLINK INNOVATIONS
AMD might well have finished with high-bandwidth multi-GPU
interconnects, but because the company isn’t currently inhabiting the high end of the graphics world, it’s easy enough to understand why it would think that they are unnecessary. Nvidia, on the other hand… Well, that’s a whole different ball game.
Although the RTX series has come with many caveats, when it comes to both price and support for as-yet unreleased and unproven game development features, one thing that is true is the ridiculous amount of data those cards can pump out at any one time. The RTX 2080 Ti, in particular, can push over 150fps in some 1080p titles alone at max settings.
When running multiples of these cards, particularly in more extreme workstation environments, having a way of transferring data across the cards simultaneously is pivotal when trying to maximize performance. And that’s exactly where NVLink originated: the server environment. In short, NVLink is a proprietary standard developed by Nvidia, which debuted back with the launch of its Pascal architecture, although the variant we know today was first seen with the Tesla V100 GPUs found inside the DGX-1 server. Each NVLink connection supports up to 50GB/s transfer rate (25GB/s each way simultaneously), well over 10 times what a single PCIe 3.0 channel can transfer, allowing for fast and seamless data throughput between the cards. The V100 cards supported up to six NVLink connections for a maximum transfer rate of 300GB/s
When it comes to mainstream cards, the RTX 2080 Ti supports two NVLink connections for a total of 100GB/s, while the RTX 2080 supports only one, for 50GB/s. Unlike SLI, NVLink doesn’t act as a display interface, merging video outputs together like a scheduler, then back through the GPU-out. Instead, thanks to its super-low latency and high bandwidth, it allows multiple GPUs to pool their resources together as a shared entity, and communicate across the bridge, reducing traffic through the PCIe bus below, making the cards more efficient.
It’s difficult to say just how much of an impact this will have on the gaming scene right now, but Hothardware.com suggests that in ShadowofWar, at 1440p, there’s as much as a doubling of performance when using NVLink versus traditional SLI, so far as scaling is concerned.