WHAT IS QUANTUM TUNNELING?
Quantum tunneling has been a headache for Moore’s Law enthusiasts for some time now, particularly in regard to processors and transistor size. In a very simplified explanation, how a transistor works (effectively flipping from 0 to 1) is that a current passes through a gate (an insulating material, or semiconducting material, in our case, silicon) that is heated up via a secondary current. As it heats up, the resistance decreases and the primary current can pass through switching that transistor from 0 (no current passing through) to 1 (current passing through).
The problem, however, is that once you get to such small transistor sizes, electrons can effectively jump through the semiconducting gate, without that gate being opened by any secondary current. That’s called quantum tunneling, and as you can imagine, creates all sorts of problems for programs that are dependent on absolute 1s and 0s.
At the moment, this is commonly seen at transistor sizes smaller than 1nm. We have seen some significant developments in the field to attempt to get around this right now. However, nothing concrete has arrived just yet that’s economically viable.
Instead, scalability and multi-chipset designs have been proposed to counteract this limitation by simply increasing the physical size of processors, but with a
caveat of increased heat and power-draw as a result.
At this point, until quantum tunneling has been sidestepped with traditional methods, brute-forcing
and double transistor size is effectively out of the question. Manufacturers will need to work smarter, not harder in how they approach their CPU and GPU designs.