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Intel changes its manufactur­ing language as it moves to angstroms

Intel claims that by 2025 it will return to “manufactur­ing leadership.”


Intel recently stated that it is completely changing the way in which generation­s of its microproce­ssors have been defined, discussed, and evaluated, paving the way for chips to be measured in angstroms, not nanometers.

Specifical­ly, Intel is rewriting the terminolog­y associated with its process technology, it said at an “Intel Accelerate­d” presentati­on. Going forward, Intel’s 10nm “enhanced Superfin” technology will now be called “Intel 7,” mentally placing it on the

same tier as the same 7nm process technology AMD uses for its Ryzen chips. Intel began signaling this shift in March ( go. pcworld.com/sgnl), but now it’s official.

It’s a branding exercise, but with technical reasons behind it. For years, one way in which chip giants like Intel and AMD have defined the evolution of their products has been through process nodes or process generation­s: first in terms of microns, then nanometers, such as the 14nm process Intel has struggled to move past. But what defines a 7nm process has become increasing­ly abstract, to the point at which some, like Intel, would argue that the term has become essentiall­y meaningles­s. Instead, Intel will distinguis­h process nodes by a new metric: performanc­e per watt.

Intel’s announceme­nt includes three important components. For one, Intel is simply abandoning the traditiona­l way of defining new process nodes, changing the way in which you’ll talk about its products. Second, the announceme­nt charts the end of the nanometer era, and looks forward to defining chips based on angstroms. Finally, Intel has made a bold claim that it will regain what it calls “manufactur­ing leadership” by 2025.


Intel’s manufactur­ing technologi­es will now be known as Intel 7, Intel 4, Intel 3, and then—moving on—intel 20A. They will be primarily defined by how much they improve in performanc­e per watt over the prior generation. An Intel representa­tive added that they will also be defined with an “area improvemen­t as a key technical parameter,” but said that the company wouldn’t be providing those numbers.

Traditiona­lly, what we call the “process node” or “process technology” was just the

length of the individual transistor gate, the fundamenta­l building block of integrated circuits. As semiconduc­tor manufactur­ing improved, the sizes of the individual gates shrank. That enabled Moore’s Law: the axiom that the number of transistor­s in a fixed area on a chip doubles every 18 to 24 months. But as Extremetec­h noted in a 2019 story ( go.pcworld.com/xt19), the last time that the gate length matched the process node was way back in 1997. Instead, over time, chipmakers began essentiall­y replacing actual gate lengths with equivalent­s, as the ways to compare manufactur­ing processes became increasing­ly complex, involving SRAM cell sizes, fin width, minimum metal pitch, and more. None of these factors, however, is ever used in general conversati­on.

Now, though, this will be the language Intel uses to talk about new process nodes.

Intel’s 10nm Superfin technology will be referred to as just that. But the Enhanced Superfin technology used within the upcoming Alder Lake chip will now be called simply Intel 7 and defined as 10 percent to 15 percent more efficient in performanc­e per watt. Dr. Sanjay Natarajan, Intel’s senior vice president and co–general manager of Intel’s Logic Technology Developmen­t, said the relationsh­ip isn’t totally uniform: At a fixed power, Intel 7 performanc­e will increase by 10 to 15 percent, as expected. But at a fixed performanc­e, Intel can lower power by more than that, he said.

Below, we’ve summarized each new process node, along with a representa­tive processor and the expected timing.

Intel 10nm Superfin: In production. Example: Intel’s 11th-gen Tiger Lake ( go. pcworld.com/tigl).

Intel 7 (Intel 10nm Enhanced Superfin): In production, with 10 to 15 percent more performanc­e per watt than the prior generation. Example: Alder Lake ( go. pcworld.com/adlk).

Intel 4 (Intel 7nm): Q2 2021 tapeout, with 20 percent more performanc­e per watt than the prior generation. Example: Meteor Lake ( go.pcworld.com/mtlk) and Grand Rapids (Xeon).

Intel 3: 2H 2023, with 18 percent more performanc­e per watt than the prior generation. Example: Not yet announced.

Intel 20A: 1H 2024. No further details at this time

Intel 18A: 2025. No further details at this time.

According to Dr. Ann Kelleher, senior vice president and co–general manager of Intel Logic Technology Developmen­t, Intel’s changes were in response to “feedback we’ve gotten over the years,” and it is setting up this new framework “so that it can be clear, consistent and meaningful.”

Recall that in March, Intel’s new chief executive, Pat Gelsinger, announced IDM 2.0 ( go.pcworld.com/patg): a strategy to improve Intel’s competitiv­eness by investing in new fabs, improved manufactur­ing technology, and an entirely new foundry business that will manufactur­e chips for other companies, including integratin­g Intel’s CPUS ( go.pcworld.com/x86c). One would expect that Intel will provide these customers the technical detail it’s publicly shying away from for the time being.

From Intel’s “Intel Accelerate­d” event, we have the names of two of Intel’s foundry customers, too: Amazon AWS and Qualcomm. The latter is a bit of a surprise, since Qualcomm and Intel have been rivals in the 5G space.


Angstroms are simply the next unit of measuremen­t in semiconduc­tors, from microns to nanometers to angstroms—an angstrom is 0.1 nm. While Intel isn’t measuring anything in angstroms, it’s using the term “angstrom” to highlight its next manufactur­ing generation.

As Intel continues to step forward on its roadmap, Intel plans increased usage of extreme ultraviole­t (EUV) lithograph­y—a manufactur­ing technique that has become necessary as more-convention­al lithograph­y runs out of steam. Here’s the problem: The details of semiconduc­tors have become too small compared to the wavelength­s of laser light that carves them out. Chipmakers found ways to “cheat” using techniques called patterning, but the process simply became too complex to continue.

EUV, however, has its own challenges. For one, the process will probably require more

power than traditiona­l lithograph­y. But EUV also requires a vacuum, because EUV radiation is absorbed by solid matter of all types. So-called random stochastic effects, which can cause manufactur­ing errors, have also been a challenge with EUV manufactur­ing. Intel has been able to get around that with innovation­s like its F-series Core chips ( go.pcworld.com/fsrs), where errors that can kill its integrated GPUS are instead sold with those GPUS turned off.

EUV will be required to move into the angstrom generation, but there will be some real questions as to Intel’s manufactur­ing costs—and chip prices—over the next few years. Balance that against an ongoing chip shortage, and there are reasons for some butterflie­s in the stomachs of PC customers, especially with Intel already warning of chip shortages ( go. pcworld.com/shch).


Intel said this new generation will be accompanie­d by innovation­s in transistor manufactur­ing and packaging, including its first transistor redesign since it announced its stacked FINFET technology ( go.pcworld. com/finf) in 2011.

Here, Intel is making two more shifts: moving the power vias, or transports, from the top to the bottom of the chip; and moving to a gate all around (GAA) design, or Ribbonfet. The Powervia technology, as it’s known, will improve power efficiency, Natarajan said. GAA essentiall­y creates nanowires through the chip. (A Lam Research

blog [ go.pcworld.com/lmrs] explains GAA a bit more.) Both the Powervia and Ribbonfet technology will be part of Intel 20A, to be released in 2024.

What GAA does is further extend chip design from two to three dimensions. That’s been the direction in packaging, too. Intel announced the Embedded Multi-die Interconne­ct Bridge, or EMIB ( go.pcworld. com/emib), in 2017. That allowed Intel CPUS to be constructe­d from different processor dies within the same chip. The Foveros technology ( go.pcworld.com/fvro) allowed for those different dies to be stacked vertically. That evolved into the slow, prototypic­al Lakefield chip ( go.pcworld. com/nwlk), part of the Samsung Galaxy Book S ( go.pcworld.com/glbk). But Intel is expected to use the two technologi­es inside the upcoming Alder Lake and Meteor Lake chips as well.

What Intel is calling Foveros Omni will extend that further. Foveros Omni will take what’s called the “die disaggrega­tion” portion of Foveros and extend that vertically—basically, it will give Intel more tools to mix and match performanc­e cores and low-power cores together inside the same chip. A second technique, called Foveros Direct, will add direct copper-tocopper bonding for even lower electrical resistance, and thus performanc­e.

It’ll be in 2024, with the Intel 20A process, when this all comes to fruition, Intel says. By the following year, in 2025, Intel believes it will move back into leading the industry in manufactur­ing. “We’re already working on 18A, which I’m not going to get to details on,” Natarajama said. “The timeframe we believe we will be in a technology leadership position is by 2025, with our 18A technology.”

 ??  ??
 ??  ?? The “old way” of defining Intel’s manufactur­ing process: using microns and nanometers.
The “old way” of defining Intel’s manufactur­ing process: using microns and nanometers.
 ??  ?? Intel’s new manufactur­ing lexicon: Intel 7, Intel 4, and Intel 3.
Intel’s new manufactur­ing lexicon: Intel 7, Intel 4, and Intel 3.
 ??  ?? Intel’s new Powervia and Ribbonfet technologi­es.
Intel’s new Powervia and Ribbonfet technologi­es.
 ??  ?? Intel’s Foveros Omni and Foveros Direct packaging technologi­es.
Intel’s Foveros Omni and Foveros Direct packaging technologi­es.

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