Western Digital’s RISC-V designs

SWERV CPU plans appear on Github.

western Digital announced it would be building its own processor, based on the open source RISC-V architecture, back in December 2018. Designs for the SWERV cores are now available on the company’s Github at https://github.com/ westerndigitalcorporation/swerv_eh1 , under an Apache 2.0 licence.

These Register-transfer Level (RTL) abstractions enable advanced users to model the CPU using the System on a Chip (SOC) modelling tool Verilator. WD stated that its rather ambitious goal is to ship one billion RISC-V cores per year through its comprehensive array of storage products. It also plans to release a FOSS RISC-V instruction set simulator, which will undoubtedly be of benefit to the wider community in the long run. Specs-wise, the SWERV core is a 32-bit in-order affair which can be clocked up to 1.8GHZ and is built on a 28nm process. It’s expected to be deployed in SSD and flash controllers rather than as a general-purpose CPU.

Western Digital’s white paper on the subject, available at http://bit.ly/lxf248wd, discusses the flexibility of RISC-V and states that “today’s general purpose architectures have reached their limit. Applications which require analytics, machine learning, artificial intelligence and smart systems demand purpose-built architectures”.

Such applications demand a scale that makes licensing ARM designs an untenable proposition, or at least a financially unrealistic one. The RISC-V instruction set architecture (ISA) can be tweaked to suit applications, and in the future we’re likely to see SWERV cores in security products, IOT devices and edge computing.