RISC heads for the Linux desktop
Apple strikes out with its own desktop Arm processors, and the world will likely follow, in its own way.
Back at the end of June 2020 Apple made the not entirely unexpected announcement that it’ll eventually be ditching all Intel processors for a CPU architecture of its own design. As you may know, since 2010 Apple has been using its own in-house designed Arm-based mobile processors to power its iphone and ipad devices.
The evolution of these processors has delivered substantial speed increases generation over generation to the point that they could challenge low-end Intel desktop processors a number of years ago, while the latest designs were as fast in single-core results as high-end Intel cores. So it’s no surprise Apple would move to create its own desktop processors.
While initial reports seemed to indicate Apple Arm devices would be entirely locked down, our own Jon Masters reported that this may in fact not be the case, which is good as the Linux and FOSS world has been running Arm-compiled software for years. So will the 2020s see a move to mainstream RISC desktops? In certain ways Linux is already there. Ignoring the Linux-running, Risc-based supercomputer installations that rule the top ten, Amazon has its own custom-designed Arm server SOC, the Graviton 2. It’s a 64-core SOC with 42MB of cache, running at 2.5GHZ with 8-channel DDR43200 memory and 64 PCIE v4 lanes on the 7nm TSMC process – serious stuff. Estimates put power use at 100W vs 210W for a similarly pegged Xeon processor.
More down to earth, there are various Armbased Chromebooks and laptops at the budget and mid-range market segments. The original Asus Flip C101 used a Rockchip RK3399 SOC, as does the very capable Pinebook Pro. It even gets a tentative thumbs up from the FSF (www.fsf. org/resources/hw/single-board-computers).
But what of RISC-V? While it seemed it may have languished in embedded systems and cheap single-board computers, Alibaba has announced its first RISC-V, design the Xuantie-910 – a 16-core SOC designed to run between 2.0GHZ and 2.5GHZ on a 12nm process. With a 12-stage pipeline, out-of-order execution, 3-stage decode, 8-issue-a-cycle execution with vector engine and 128KB L1 cache, it claims this is the fastest RISC-V design ever.
This all points to innovative, low-power designs coming through, and they’ll all be Linuxready. It’ll just depend if there’s a consumer standard that enables user freedom as the PC standard currently does.