Special Interest

The basic PCIe specification is handled by a SIG (special interest group) of the big PC players, including Intel, IBM, and around 700 others. The plan was to replace the PCI, PCI-X, and AGP bus (although it looks as though it’ll replace more). PCIe 1.0 was nailed down in 2003. It runs at 250MB/s per lane. Version 1.1 brought technical improvements. In 2007, we got version 2.0, which doubled the data rate by simply doubling the clock to 5GHz. Again, this was soon followed by a technically improved version 2.1. PCIe 2.0 first appeared on Intel’s X38 chipset, and is still in circulation in the H110, X79, and X99 chipsets.

The current version 3.0 appeared in 2010, and nearly doubles performance again, to 8Gb/s or 985MB/s, thanks to a clock jump to 8GHz, and more efficient encoding. Version 3.1 brought some technical housekeeping. All versions of PCIe have been backward compatible, which is a joy.

Version 4.0? Not far away now. The specifications were announced in 2011, and again we get a doubling of the data rate. We saw test machines running experimental silicon last year, and were promised it for 2017. However, things have gone a little quiet now. Technically, it has proved harder than anticipated— this sort of data rate down a copper wire is skirting the edge of practicability. There have been no press releases on the PCI SIG website this year at all. If it does appear this year, it will be late; 2018 looks more likely. Luckily, we aren’t banging on the limits of version 3.0 yet.

Beyond this, we have talk of version 5.0. Once again, we’ve been promised alarming data rates of 25 or even 32Gb/s. This used to mean optical, although recent developments in Ethernet technology mean that we may have one more copper, or partly copper, version left.