A step-by-step lowdown on the basic flow of FPGA designing for new design engineers
Field- programmable gate array (FPGA) is a device that has numerous gate (switch) arrays and can be programmed on-board through dedicated -oint Test Action Group (-TAG) or on-board devices or using remote system through Peripheral Component Interconnect Express (PCIe), Ethernet, etc. FPGAs are based on static random- access memory (S5AM). The contents of the memory of an FPGA erase once the power is turned off. Usually, FPGAs can be programmed several thousands of times without the device getting faulty.
Fig. 1 shows the architecture of an FPGA. It includes logic blocks, input/ output (I/O) cells, phase-locked loops/ delay-locked loops (PLLs/DLLs), block 5AM and interconnecting matrix. Nowadays, FPGAs are also coming up with several hard intellectual property (IP) blocks of PCIe, Ethernet, 5ocket I/O, PHYs for DD53 interfaces and processor cores (for example, PowerPC in Xilinx Virtex- FPGA and A5M cores in both Xilinx and Altera series FPGAs).
To level up with the new technology, both Xilinx and Altera have come up with new series of FPGAs (Virtex 7 from Xilinx and Stratix-V from Altera), which are manufactured with TSMC’s 28nm silicon technology. These FPGAs focus on a high speed with low power consumption using various parameters and bringing down the FPGA core voltage to as low as 0.9V. Along with the new FPGAs, Xilinx and Altera are also focused on improving their synthesis tools to meet the routing constraints and to analyse the timing and power consumption of the FPGA.
As the aim here is to learn the basic technique of FPGA design to work with both the tools and devices, let’s get back to the design ow through the steps.
Step 1: Requirement analysis and SRS preparation
Before starting work on the design, all requirements should be documented as system requirement specification (S5S) by designers and approved by various levels in the organisation, and most importantly, the client. During this phase, FPGA designers, along with the hardware team, should identify suitable FPGAs for the proMect. This is very important because designers need to know parameters such as the I/O voltage levels, operating frequency and external peripheral interfaces.
It is also important to determine which IP cores are available with the tools or FPGA family used for the pro- Mect. Some IP cores are free, while others are licensed and paid for. This cost should be reviewed several times by the team before releasing it to the client and listed separately for approval from the client or management.
The S5S should contain the following (the list pertains to the FPGA only) 1. Aim of the proMect 2. Functionalities to be handled by the design, followed by a short description
3. A concept-level block diagram depicting the maMor internal peripherals/IPs of the FPGA
4. FPGA vendor, family, speed grade, package, core voltage, supported I/O levels, commercial/industrial type
. List of blocks that will be used as IPs. Mention clearly what’s available for free with the vendor-provided IPs, hard IPs available within the FPGA