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are com­pat­i­ble with mul­ti­ple FPGA prod­uct fam­i­lies.”

Ahuja says, “While the use of com­mer­cial and in-house IP can re­duce the over­all cost of the de­sign, in­te­gra­tion is a chal­lenge and there has been an in­crease in the cost to in­te­grate var­i­ous IP blocks into a com­plex SoC ar­chi­tec­ture. These costs continue to rise with each new gen­er­a­tion of SoC largely driven by the dra­matic in­crease in the num­ber of IP blocks in­fused into the ar­chi­tec­ture.”

AnRWHHU DVSHFW WR FRVW DnG SUR­fiWa­bil­ity is the amount of ef­fort made by the sil­i­con de­sign­ers to cre­ate the ad­vanced SoC ar­chi­tec­tures expected by end-users for each new gen­er­a­tion of sil­i­con.

The IP ecosys­tem needs to change so that SoC de­sign can adopt a sys­tem­level-driven ap­proach to re­solve is­sues like those men­tioned above. The IP must be de­signed from a sys­tem-level point of view from the very be­gin­ning in or­der to make it eas­ier for the sil­i­con ar­chi­tect to adopt and use in his de­sign. At the same time, the IP must al­low for ease of in­te­gra­tion into the de­sign.

Ac­cord­ing to Gupta, for de­sign teams driv­ing early adoption of new tech­nol­ogy nodes, ex­pense man­age­ment does not di­rectly play a role in the de­ci­sion to go for an IP from a third-party ven­dor. It is typ­i­cally the na­ture of the IP, the lim­ited re­sources inside, the tight time­lines of projects, and the ex­per­tise and his­tory of the IP ven­dor that drive the de­ci­sion.

How­ever, once the IP on a par­tic­u­lar tech­nol­ogy node has been tried and tested and the process tech­nol­ogy node has be­come main­stream, ex­pense man­age­ment in terms of de­vel­op­ment re­sources re­quired, the costs in­volved and the sched­ules in­volved start to play a huge role. The ma­jor chal­lenge is not nec­es­sar­ily the de­sign of the IP EXW UDWHHU WHH vHUL­fiFDWLRn DnG vDOLGD­tion of the IP to en­sure that it works SHUIHFWOy finH WR WHH GHVLUHG VSHFL­fiFD­tions.

Thus the value of an IP that has been used a few times by other cus­tomers is very high. It gives the de­sign WHDP WHH FRn­fiGHnFH UHTXLUHG nRW RnOy in the IP it­self but also in the fact that oth­ers have suc­cess­fully in­te­grated that IP into their own de­sign en­vi­ron­ments to de­velop their chips. It dra­mat­i­cally low­ers the risks in­volved and be­comes a no-brainer on ex­pense re­duc­tion com­pared to in-house de­vel­op­ment.

Key play­ers out­sourc­ing IP

One other as­pect to note is that the key play­ers are now able to in­creas­ingly out­source IP.

Ac­cord­ing to Peckham, the adoption of in­dus­try stan­dards as al­ready men­tioned to­gether with a tool suite such as sivado De­sign Suite from Xil­inx—which sup­ports mul­ti­ple lan­guages such as sHDL, ser­ilog and Sys­tem-ser­ilog in the HDL do­main, C, C++, Sys­tem C and Si­mulink mod­el­based de­sign in the ESL do­main—are all developments that have fa­cil­i­tated in­creas­ing lev­els of out­sourc­ing.

Ac­cord­ing to Ahuja, an im­por­tant trend is that large semi­con­duc­tor com­pa­nies which would have pre­vi­ously rarely con­sid­ered pur­chas­ing ex­ter­nal IP ex­cept for per­haps an ARM core, are now chang­ing their strat­egy and be­gin­ning to em­brace ex­ter­nal IP. One of the key en­ablers of this trend is the pro­to­col IP space, as this re­moves the need to in­vest in­ter­nally and cre­ates a piece of IP that is de­signed to meet a SDUWLFXODU VSHFL­fiFDWLRn. ,nVWHDG, EXy­ing it off-the-shelf can help to ver­ify its

Giles Peckham EMEA Mar­ket­ing Di­rec­tor,Xil­inx Inc.

Anil Gupta Manag­ing Di­rec­tor, Ap­plied Mi­cro Cir­cuits In­dia

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