MAJOR CONTRIBUTORS TO THIS REPORT
are compatible with multiple FPGA product families.”
Ahuja says, “While the use of commercial and in-house IP can reduce the overall cost of the design, integration is a challenge and there has been an increase in the cost to integrate various IP blocks into a complex SoC architecture. These costs continue to rise with each new generation of SoC largely driven by the dramatic increase in the number of IP blocks infused into the architecture.”
AnRWHHU DVSHFW WR FRVW DnG SURfiWability is the amount of effort made by the silicon designers to create the advanced SoC architectures expected by end-users for each new generation of silicon.
The IP ecosystem needs to change so that SoC design can adopt a systemlevel-driven approach to resolve issues like those mentioned above. The IP must be designed from a system-level point of view from the very beginning in order to make it easier for the silicon architect to adopt and use in his design. At the same time, the IP must allow for ease of integration into the design.
According to Gupta, for design teams driving early adoption of new technology nodes, expense management does not directly play a role in the decision to go for an IP from a third-party vendor. It is typically the nature of the IP, the limited resources inside, the tight timelines of projects, and the expertise and history of the IP vendor that drive the decision.
However, once the IP on a particular technology node has been tried and tested and the process technology node has become mainstream, expense management in terms of development resources required, the costs involved and the schedules involved start to play a huge role. The major challenge is not necessarily the design of the IP EXW UDWHHU WHH vHULfiFDWLRn DnG vDOLGDtion of the IP to ensure that it works SHUIHFWOy finH WR WHH GHVLUHG VSHFLfiFDtions.
Thus the value of an IP that has been used a few times by other customers is very high. It gives the design WHDP WHH FRnfiGHnFH UHTXLUHG nRW RnOy in the IP itself but also in the fact that others have successfully integrated that IP into their own design environments to develop their chips. It dramatically lowers the risks involved and becomes a no-brainer on expense reduction compared to in-house development.
Key players outsourcing IP
One other aspect to note is that the key players are now able to increasingly outsource IP.
According to Peckham, the adoption of industry standards as already mentioned together with a tool suite such as sivado Design Suite from Xilinx—which supports multiple languages such as sHDL, serilog and System-serilog in the HDL domain, C, C++, System C and Simulink modelbased design in the ESL domain—are all developments that have facilitated increasing levels of outsourcing.
According to Ahuja, an important trend is that large semiconductor companies which would have previously rarely considered purchasing external IP except for perhaps an ARM core, are now changing their strategy and beginning to embrace external IP. One of the key enablers of this trend is the protocol IP space, as this removes the need to invest internally and creates a piece of IP that is designed to meet a SDUWLFXODU VSHFLfiFDWLRn. ,nVWHDG, EXying it off-the-shelf can help to verify its
Giles Peckham EMEA Marketing Director,Xilinx Inc.
Anil Gupta Managing Director, Applied Micro Circuits India