NEW RESEARCH ON MEMORY ARCHITECTURES

Researchers at the Indian Institute of Technology (IIT) Guwahati have made fundamental contributions to memory architectures by preventing redundancy in data values and improving slow and frequent writes in the multi-core processor systems. When the world is rapidly moving towards research in applied areas, IIT Guwahati researchers have developed methods to solve the problems in computer systems domain.

Specific contributions being in multi-core processor-based systems that need an equally large on-chip memory to commensurate the data demands of the ever-growing applications and hence preventing energy consumption to ensure the temperature remains under the thermal design power (TDP) budget.

The research is being led by Prof. Hemangee K. Kapoor, department of computer science and engineering (CSE), IIT Guwahati, and comprises a team of research scholars: Sukarn Agarwal, Palash Das, Sheel Sindhu Manohar, Arijit Nath and Khushboo Rani. The findings of their research are published in reputed peer-reviewed journals like IEEE Transactions on Computers, IEEE Transactions in VLSI, IEEE TCAD, ACM Transactions on Embedded Computing Systems, ACM TODAES, ACM JETC, to name a few. Explaining the challenges of multi-core processor-based systems, Kapoor said, “The application data access patterns are not uniformly distributed and hence leads to several orders of writes to certain memory locations compared to others. Such heavily written locations become prone to wearing out and thus prevents the use of complete memory device without error corrections”.

To handle this non-uniformity, IIT Guwahati researchers developed methods to evenly distribute the accesses across the overall memory capacity to reduce the wearing out pressure on heavily written locations and also worked in the area which avoids writing redundant values thus prolonging wear-out.