SynopSyS’ new uSB 2.0 Type-c ip cuTS power and area for ioT edge applicaTionS

Synopsys announced that it has reduced the power and area of its DesignWare USB 2.0 Type-C Controller and PHY IP for cost-sensitive and energy-efficient Internet of Things (IoT) edge applications targeting 40-nanometer (nm) and 55-nm ultra-low power processes. The IP cuts silicon area by up to 50 percent compared to competitive offerings, saving on average $0.03 per die. To extend battery life, the USB IP uses 30 percent lower active power compared to competing solutions and near 0 W of standby power. The DesignWare USB 2.0 Type-C IP supports the IEEE 1801 standard Unified Power Format (UPF) to speed implementation and testing of power domains. In addition, Synopsys has simplified configuration options in the IP to reduce integration and verification effort by weeks or months.