Zen 3 Aims to Keep AMD CPU Momentum Rolling
OVER THE PAST SEVERAL YEARS, AMD’s CPU team has been firing on all cylinders. Or cores.... It has pushed Intel in ways that were almost forgotten. And AMD is not letting up on the pressure, either. In its recent Financial Analyst Day briefings, AMD went i
Zen 3 and fourth-gen Ryzen CPUs are coming and should launch by the end of the year.
The most important bits: Yes, Zen 3 and fourth-gen Ryzen CPUs are coming and should launch before the end of the year. Plus, RDNA 2 and Navi 2x GPUs with ray-tracing capabilities will also arrive before 2021. I’m going to leave the GPU discussion for another day and focus on the Zen 3 CPUs.
First, Zen 3 will continue to use TSMC’s 7nm FinFET manufacturing process. There were earlier rumors that it would switch to TSMC’s N7+ Extreme Ultraviolet (EUV) node—and it still might—but AMD has stopped referring to it as “7nm+” and now just calls it 7nm. That doesn’t mean it’s the same node as Zen 2, however, as TSMC has a newer secondgen N7P “performance-enhanced” node available that sticks with Deep Ultraviolet (DUV).
N7P is design compatible with the original N7, but optimizations allow TSMC to deliver either 7 percent higher boost performance (clock speeds) at the same power, or keep the same performance and reduce power use by 10 percent. N7+ is not design compatible, but offers larger potential gains: It allows for 15–20 percent better density than N7, so more transistors can be crammed into a chip, or chips can be smaller. Whether it uses EUV N7+ or DUV N7P, Zen 3 should see at least modest improvements on the silicon side of things.
AMD will also be updating the base architecture, as it always does, but it hasn’t revealed too many details. Most of what we know comes from the data center side of things, where the 7nm Zen 3 “Milan” CPUs will feature a modified Core Complex (CCX) compared to previous Zen architectures. The biggest change is that instead of having two fourcore CCX partitions in a chiplet with 16MB of L3 cache each, Zen 3 will have a unified eight-core CCX with a shared 32MB L3 cache. That’s important as it should improve latency and memory throughput, which improves performance.
Going back to the original Zen architecture, AMD’s CCX has been both good and bad. Having a simplified building block that can be repeated as needed is great for scaling to higher core counts, and it reduces time to market and overall chip complexity. It’s a major part of why AMD was able to launch eight-cores with first and second-gen Ryzen, then up to 16-cores with third-gen Ryzen. However, the partitioned L3 cache CCX approach does add latency to any cache accesses that have to cross from one CCX to the other. Zen 2 helped overcome this by doubling the L3 cache size, and Zen 3 will improve things further by unifying the L3 cache for each chiplet. There will still be added latency for cross-chiplet cache accesses, but the sheer size of the L3 caches will help to combat that.
There are also reports that Zen 3’s floating point performance could be up to 50 percent higher than in Zen 2, with instruction per clock (IPC) gains from 8–17 percent, depending on workload.
This is all at the same power requirements as Zen 2. These chips are already easily beating Intel’s best when it comes to performance per watt. It desperately needs something better than 14nm+++ CPUs if it hopes to compete.
Jarred Walton has been a PC and gaming enthusiast for over 30 years.